The present invention relates to a power amplifier having an input connected to a main port of a quadrature hybrid splitter, said quadrature hybrid splitter having an in-phase port coupled to an output of said power amplifier through a main amplifier and another quadrature hybrid, said quadrature hybrid splitter further having a 90° phase shift port also coupled of said other quadrature hybrid.
Such a power amplifier PA is already known in communication systems, such as Global System for Mobile communications/Enhanced Data rates for GSM Evolution GSM/EDGE, code-division multiple-access CDMA2000, wide-band code-division multiple-access W-CDMA and Long Term Evolution LTE, where it is required to operate with high efficiency and high linearity simultaneously.
However, there is a tradeoff between efficiency and linearity with improvement in one coming at the expense of another. Generally, the basic linearization approaches are based on analog and digital correction techniques. Conventional base station architectures usually contain power amplifiers, which generate output power levels of 100 W and higher in two single transistor elements.
To linearize such PAs, usually Digital PreDistortion DPD is applied. Digital linearization systems require digital adaptive processing based on periodically updated look-up tables and feedback path to be able to properly react to changes due to the load, process, temperature, or supply voltage variations. The correction factors for amplitude and phase computed using the adaptation algorithm are stored in the look-up tables, and are dynamically updated to reduce errors between the predistorter input and the power amplifier output. However, a substantial linearity improvement comes without incurring a bandwidth limitation when the power amplifier can be considered memoryless, which is not the case for wideband telecommunication standards like CDMA200 or WCDMA.
As said, the complexity of the adaptive digital predistortion system is a serious drawback because it is implemented with considerable computing power of a digital signal processor. For adaptive predistortion, it is also necessary to carefully model the power amplifier transfer characteristic. DPD is a very effective and efficient linearization method, if the computational effort, the cost and energy consumption of the sampling receiver, the large bandwidth of the transceiver chain and the resulting complexity of the diplexer filter are in a low ratio compared to the generated RF-power levels. Usually for high-power-applications in the order of several ten or even 100 Watts this is the case. But as soon as the number of power amplifiers in a base station increases, as it is the case in distributed and active antenna applications, this effort gets prohibitively expensive: e.g. in an active antenna for macro-base-station applications the number of transceiver elements is about eight to ten. To install an individual Digital PreDistortion-Field Programmable Gate Array DPD-FPGA, an individual sampling receiver and a complex duplex filter in each antenna element is prohibitive in terms of form factor, cost and weight. In such cases an alternative, cheap, efficient and effective linearization method has to be applied. The proposed method is of such a kind: it is an analog linearization method with increased efficiency and low implementation cost.
Existing feedforward power amplifiers which improve linearity already exist, but those are of inherently low efficiency. Such a basic analog linearization solution represents a feedforward power amplifier configuration which block schematic is shown at FIG. 1. The feedforward power amplifier system includes the main amplifier (MA11), three couplers (the quadrature hybrid splitter (SP11), a subtracter (SU11), and the other quadrature hybrid (CO11) that is a combiner), two phase shifters (PH11, PH12), two attenuators (AT11, AT12), and error amplifier (EA11).
The operation of the feedforward linearization circuit is based on the subtraction of two equal signals with subsequent cancellation of the error signal in the amplifier output spectrum. Its operation principle can be demonstrated by the two-tone test spectra at various points of the block diagram. The input signal is split to form the two identical parts, although in a common case the ratio used in the splitting process does not need to be equal. Then, a portion of the main amplifier output signal coupled by the coupler-subtracter is subtracted from a time-delayed and opposite phase portion of the original signal to remain an error signal only. The result of this subtraction is an error signal that ideally contains nonlinear distortion only generated by the main amplifier. The error signal is then amplified linearly to the required level in order to cancel the distortion in the main part and fed to the output combiner, on the other input of which a time-delayed and opposite-phase main-path signal is forwarded.
The resulting signal at the feedforward linearization system output is an error-free signal and an amplified version of the original input signal. However, efficiency in this feedforward system is very low because the power consumption of the error amplifier is significant in order to obtain the required error signal at the output. In addition, the phase shifter and attenuator at the output path make a significant contribution to the overall system power loss.